ADDRESS DECODER

When memory chips are bought, they are not mapped to any particular memory address. As we all know, each chip contains so many cells (i.e. addresses) to hold bits. The general layout for a memory chip is as follows:

Addess bus lines ------------à ||||||||||||||||||||||||||||||||

(Enough to ||||||||||||||||||||||||||||||||

identify each cell ||||||||||||||||||||||||||||||||

in the memory chip) ||||||||||||||||||||||||||||||||

||||||||||||||||||||||||||||||||

Data bus -----------à ||||||||||||||||||||||||||||||||

R/W line -----------à ||||||||||||||||||||||||||||||||

Chip Select -----------à ||||||||||||||||||||||||||||||||

The data bus is a bi-directional bus that holds either the data going to or the data coming from the memory chip. The R/W line determines if the chip is going to take data from the data bus or release data to the data bus. The chip select line is a line that, when high (1), “wakes up” the memory chip. When this line is low(0), the chip is essentially “asleep” and ignores any electrical impulses coming into it.

An address decoder is a circuit that takes signals from the address bus and outputs the Chip Select lines. The following simple example illustrates an address decoder for a computer system that has only 16 bytes of memory that is composed of (4) 4-byte memory chips. For this case, the address bus will be 4-bits ( A4 A3 A2 A1) to represent the 16 memory address 0 – 15.l

Add. 0 -3 Add. 4-7 Add. 8-11 Add. 12-15

Chip 0 Chip 1 Chip 2 Chip 3

|||||||||||||||| ||||||||||||||||| |||||||||||||||||| |||||||||||||||||||

data bus---à |||||||||||||||| ||||||||||||||||| |||||||||||||||||| |||||||||||||||||||

R/W line -à |||||||||||||||| ||||||||||||||||| |||||||||||||||||| |||||||||||||||||||

A2 A1----à ||||||||||||||| ||||||||||||||||| |||||||||||||||||| |||||||||||||||||||

^ ^ ^ ^

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Chip Chip Chip Chip

Select 0 Select 1 Select 2 Select 3

Chip Select 0 (that comes out of the address decoder), should be a (1) if addresses 0 – 3 are on the address bus. If one would think of these addresses in binary, one would notice that have some in common (i.e. the leftmost two bits are 00 )

0 0000

1 0001

2 0010

3 0011

Thus, Chip Select 0 should be (1) if A4 and A3 are both zeroes. This can be described by the following logic equation: Chip Select 0 = Not A4 and not A3

This equation will only produce one if A4 and A3 are both zeroes.

Similar logic can be applied to create the other chip selects whiach are as follows:

Chip Select 1 = not A4 and A3

Chip Select 2 = A4 and not A3

Chip Select 3 = A4 and A3

The low part of the address bus (A2 A1) go directly to the chip so that it can uniquely identify one of the four cells in the chip. The chip will ignore these inputs if the chip select line is low (0).